Semiconductor memory device

ABSTRACT

A semiconductor memory device includes first and second MOS transistors connecting a pair of data lines with a specific potential supplying node. A power transmitting circuit couples the specific potential supplying node with a power supply circuit of an equalizing potential after said first and second switching elements are made conductive. The power transmitting circuit isolates the specific potential supplying node from the power supply circuit when the equalization begins. As an alternative to the power transmitting circuit, a supplying circuit may be connected to supply a precharge potential to the specific potential supplying node when the equalization begins, and supply an equalizing potential to the specific potential supplying node when the switching elements are both turned on.

This is a Division of application Ser. No. 08/371,536 filed Jan. 11,1995 now U.S. Pat. No. 5,477,496.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory device of a highpacking density, such as a dynamic random-access memory (hereinafterreferred to as DRAM), and in particular to a precharge and equalizationcircuit for quickly bringing a pair of data lines to a fixed potential.

An example of conventional equalizing circuit is shown U.S. Pat. No.5,036,492. The equalizing circuit is formed of two transistors providedbetween a pair of bit lines connected to a precharge circuit forsupplying a predetermined potential. The two transistors have theirsources connected respectively to the data lines their drains connectedwith each other, and their gates to which complementary equalizingsignals are supplied. A bleeder current device is also connected to thedrains. With such a configuration, the two transistors are concurrentlyactivated, by means of the complementary equalizing signals, to set thebit lines at a same potential. The bleeder current device absorbs orsupplies current so that the potentials on the bit lines do not departfrom the set potential.

The above-described equalizing circuit requires a precharge circuit, andtwo control signals are required to control the precharge circuit andthe equalizing circuit, so that the control over operation iscomplicated, and it is difficult to increase the overall operation speedof the device.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the invention to simplify the controlover operation and to increase the overall operation speed of thedevice.

According to a first aspect of the invention, there is provided asemiconductor memory device comprising:

a pair of data lines for transferring complementary signals;

an equalizing circuit having a first switching element connected betweenone of said pair of data lines and a specific potential supplying node,and a second switching element connected between the other of said pairof data lines and the specific potential supplying node, said first andsecond switching elements being made conductive in accordance with acontrol signal to electrically connect said pair of data lines with eachother;

a power transmitting circuit connecting said specific potentialsupplying node with a power supply circuit of an equalizing potentialafter said first and second switching elements are made conductive;

said power transmitting circuit isolating said specific potentialsupplying node from said power supply circuit when one of said first andsecond switching elements becomes conductive and tile other of saidfirst and second switching elements is not yet conductive.

The first and second switching elements of said equalizing circuit maycomprise MOS transistors having their gate electrodes connected toreceive said control signal.

With the above arrangement, the specific potential supplying node isisolated from the equalizing potential power supply circuit when one ofthe switching elements is conductive and the other switching element isnot yet conductive, at the time when the equalization begins, i.e., whenthe control signal changes from the inactive state to the active state.As the potential of the control signal line varies (from the inactivestate toward the active state) one of the switching elements (firstswitching element) connected to one of the data lines is turned on, sothat the potential of the specific potential supplying node is variedtoward the potential of the above-mentioned one of the data lines. Whenthe potential of the control signal becomes sufficient, the switchingelement (second switching element) connected to the other data line ismade conductive. It take less time for the potential of the controlsignal to become sufficient to turn on the second switching elementbecause of the variation of the specific potential supplying node towardthe above-mentioned one of the data lines, than if the specificpotential supplying node is fixed at the equalizing potential. Thus, thetwo switching elements are made conductive in a shorter time, than ifthe specific potential supplying node is not isolated from theequalizing power supply circuit.

Assume that the switching elements are N-channel MOS transistors. As thepotential of the control signal line rises (above a threshold of the MOStransistor) one of the MOS transistors (first MOS transistor) connectedto one of the data lines which has transferred the signal of a lowerpotential level is made conductive to draw the charge from the specificpotential supplying node, so that the potential of the specificpotential supplying node is lowered. Because of the potential drop ofthe specific potential supplying node, the MOS transistor (second MOStransistor) connected to the data line having a higher potential is madeconductive when the potential of the control signal becomes sufficient.The potential sufficient to turn on the second MOS transistor is the sumof the threshold of the transistor and the potential of the specificpotential supplying node, which is lower than if the specific potentialsupplying node is fixed at the equalizing potential. Accordingly, theMOS transistors are made conductive in a shorter time, than if thespecific potential supplying node is not isolated from the equalizingpower supply circuit.

According to a second aspect of the invention, there is provided asemiconductor memory device comprising:

a pair of data lines for transferring complementary signals;

an equalizing circuit having a first switching element connected betweenone of said pair of data lines and a specific potential supplying node,and a second switching element connected between the other of said pairof data lines and the specific potential supplying node, said first andsecond switching elements being made conductive in accordance with acontrol signal to electrically connect said pair of data lines with eachother;

a supplying circuit connected to said specific potential supplying node,supplying a precharge potential to said specific potential supplyingnode until said first and second switching elements are turned on, andsupplying an equalizing potential to said specific potential supplyingnode after said first and second switching elements are turned on.

The first and second switching elements of said equalizing circuit maycomprise MOS transistors having their gate electrodes connected toreceive said control signal.

With the above arrangement, the precharge potential is applied to thespecific potential supplying node at the time when the equalizationbegins, i.e., when the control signal changes from the inactive state tothe active state. As the potential of the control signal line varies(from the inactive state toward the active state) one of the switchingelements (first switching element) connected to one of the data lines isturned on. The precharge potential applied to the potential (VPL or VPH)is such a value which is closer than the equalizing potential to thepotential of the data line of the above-mentioned one of the data lines.When the potential of the control signal becomes sufficient, the otherswitching element (second switching element) connected to the other dataline is made conductive. It take less time for the potential of thecontrol signal to become sufficient to turn on the second switchingelement because the specific potential supplying node is at theprecharge potential which is closer to the above-mentioned one of thedata lines, than if the specific potential supplying node is fixed atthe equalizing potential. Thus, the two switching elements are madeconductive in a shorter time, than if the specific potential supplyingnode is not isolated from the equalizing power supply circuit.

Assume that the switching elements are N-channel MOS transistors. As thepotential of the control signal line rises (above a threshold of the MOStransistor) one of the MOS transistors (first MOS transistor) connectedto one of the data lines which has transferred the signal of a lowerpotential level is made conductive. The MOS transistor (second MOStransistor) connected to the data line having a higher potential is madeconductive when the potential of the control signal becomes sufficient.The potential sufficient to turn on the second MOS transistor is the sumof the threshold of the transistor and the potential of the specificpotential supplying node, which is lower than if the specific potentialsupplying node is fixed at the equalizing potential, because thespecific potential supply node is at the precharge potential VPL, whichis lower than the equalizing potential. Accordingly, the MOS transistorsare made conductive in a shorter time, than if the specific potentialsupplying node is not isolated from the equalizing power supply circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a precharge and equalization circuitof Embodiment 1.

FIG. 2 is a waveform diagram showing the operation of the circuit ofEmbodiment 1.

FIG. 3 is a circuit diagram showing a precharge and equalization circuitof Embodiment 2.

FIG. 4 is a circuit diagram showing a precharge and equalization circuitof Embodiment 3.

FIG. 5 is a circuit diagram showing a precharge and equalization circuitof Embodiment 4.

FIG. 6 is a waveform diagram showing the operation the circuit ofEmbodiment 4.

FIG. 7 is a circuit diagram of a VPL potential generating means ofEmbodiment 4.

FIG. 8 is a circuit diagram showing a precharge and equalization circuitof Embodiment 5.

FIG. 9 is a circuit diagram showing a precharge and equalization circuitof Embodiment 6.

FIG. 10 is a waveform diagram showing the operation of the circuit ofEmbodiment 6.

FIG. 11 is a circuit diagram showing a precharge and equalizationcircuit of Embodiment 7.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the invention will now be described with reference to thedrawings. In the various figures of the drawings, identical referencenumerals denote identical or corresponding elements or components.

Embodiment 1

FIG. 1 is a circuit diagram of a precharge and equalization circuit of afirst embodiment (hereinafter called Embodiment 1) of the presentinvention.

The precharge and equalization circuit of Embodiment 1 comprises anequalizing circuit 10, which is disposed between a pair of data lines 1and 2 connected to an amplifier 3, such as a sense amplifier, viaswitches 4. The equalizing circuit 10 comprises a pair of switchingelements, in the form of N-channel MOS transistors 11 and 12 havingtheir drains connected to the data lines 1 and 2, respectively, theirsources both connected to a specific potential supplying node 14, andtheir gates connected to a control signal line 6.

The precharge and equalization circuit further comprises a powertransmitting circuit which is formed of an N-channel MOS transistor 13having a gate connected to a second control signal SE. The drain of thetransistor 13 is connected to the specific potential supplying node 14,and the source of the transistor 13 is connected to an equalizingpotential power supply circuit 5 supplying an equalizing potential HVcc(Vcc/2).

The second control signal SE makes the MOS transistor 13 non-conductivewhile the control signal 6 changes from the inactive state to the activestate, and making the MOS transistor 13 conductive after the first andsecond switching elements 11 and 12 are made conductive.

The data lines 1 and 2 are driven by the amplifier 3 via the switches 4to transfer complementary information (Vcc level or the GND (ground)level).

For reading data from a memory cell not shown, the switch 4 is turned onto drive the pair of data lines 1 and 2 by means of the amplifier 3 forthe purpose of information transfer. They are assumed to be set at theVcc level and the GND level, respectively. The control line 6 is at theLow level (GND level), so that the transistors 11 and 12 are off, andthe control signal SE is at the High level, and the transistor 13 is on,and the potential of a node 14, which is the specific potentialsupplying node, is at HVcc. After the information transfer is completed,the switches 4 are turned off to isolate the amplifier 3 from the datalines 1 and 2, and the control signal SE is brought to the Low level toturn off the transistor 13, and the potential of the control line 6 israised to the High level to commence the equalizing operation, inpreparation for the next cycle of data transfer operation. When thepotential of the control line 6 exceeds the threshold potential Vth ofthe transistor 12, the transistor 12 is turned on, and the potentiallevel of the node 14 is lowered. This is because the node 14 is isolatedfrom the power supply circuit 5, and the parasitic capacitance of thenode 14 is small compared with the data line 2 at the GND level, so thatthe charge is drawn from the node 14. Because of the lowering of thepotential level of the node 14, the gate voltage of the transistor 11becomes sufficient, i.e., exceeds the threshold, also denoted by Vth, ofthe MOS transistor 11, and the transistor 11 is turned on. As a result,the potential level of the data line 1 is lowered. Thereafter, thecontrol signal SE is raised to the High level at a predetermined timing,the node 14 is connected to the power supply circuit 5, to equalize thepotentials of the data lines 1 and 2 to HVcc.

Because the potential of the node 14 is lowered before the transistor 11turns on, it takes less time for the MOS transistor 11 to turn on, thanif the potential of the node 14 is fixed at the equalizing potentialHVcc. If the potential of the node 14 is fixed at HVcc, the MOStransistor 11 is not turned on until the potential on the control line 6exceeds HVcc + Vth (Vth being the threshold of the MOS transistor 11).Accordingly, the MOS transistors 11 and 12 are turned on in a shortertime than if the node 14 is not isolated from the equalizing potentialpower supply circuit 5. The pair of data lines are quickly equalized bymeans of a relatively simple configuration. Moreover, the number oftransistors connected to the control line 6 is two per pair of datalines, so that delay in the rise of the data lines due to the parasitismof gate capacitances can be avoided. Furthermore, increase in the powerconsumption in the equalizing circuit is small.

Embodiment 2

FIG. 3 is a circuit diagram of a precharge and equalization circuit of asecond embodiment (Embodiment 2). The precharge and equalization circuitof Embodiment 2 comprises an equalizing circuit 10 which is identical tothe equalizing circuit 10 of Embodiment 1. In place of the transistor13, a resistance element formed of a resistor 15 is provided. Thesources of the transistors 11 and 12 are both connected to one end ofthe resistor 15, and the other end of the resistor 15 is connected tothe power supply circuit 5 supplying the equalizing potential HVcc. Thedata lines 1 and 2 are driven by the amplifier 3 via the switches 4 totransfer information, like Embodiment 1.

The operation of Embodiment 2 is similar to the operation ofEmbodiment 1. For instance, for reading data from a memory cell notshown, the switches 4 are on, and, for the purpose of informationtransfer, the data lines are driven by means of the amplifier 3 and set,for example, to the Vcc level and the GND level, respectively. Thecontrol line 6 is at the Low level (GND level), so that the transistors11 and 12 are off, and the potential of the node 14, is set to thepotential of the power supply circuit 5 via the resistance element 15.After the information transfer is completed, the switches 4 are turnedoff to isolate the amplifier 3 from the data lines 1 and 2, and thepotential of the control line 6 is raised to the High level to commencethe equalizing operation, in preparation for the next cycle of datatransfer operation. When the potential of the control line 6 exceeds thethreshold potential Vth of the transistor 12, the transistor 12 isturned on, and the potential level of the node 14 is lowered, becausethe parasitic capacitance of the node 14 is small compared with the dataline 2 at the GND level, and the charge is drawn from the node 14.Because of the lowering of the potential level of the node 14, the gatevoltage of the transistor 11 becomes adequate, and the transistor 11 isturned on, before the potential on the control line 6 exceeds HVcc +Vth, to lower the potential level of the data line 1. Thereafter, thepotential on the node 14 is brought to HVcc, being delayed by theresistance element 15, and the potentials of the data lines 1 and 2 areequalized to HVcc. Embodiment 2 has the advantage, in addition to thoseof Embodiment 1, that the control with the control signal SE is notnecessary.

Embodiment 3

FIG. 4 is a circuit diagram of a precharge and equalization circuit of athird embodiment (Embodiment 3). The precharge and equalization circuitof Embodiment 3 comprises an equalizing circuit 10 which is identical tothe equalizing circuit 10 of Embodiment 2. In place of the resistor 15of Embodiment 2, an N-channel MOS transistor 16 is provided. The gate ofthe transistor 16 is connected to a power supply 7 of a fixed potentialVp. The sources of the transistors 11 and 12 are connected to the drainof the transistor 16, and the source of the transistor 16 is connectedto the power supply circuit 5 supplying the equalizing potential HVcc.The data lines 1 and 2 are driven by the amplifier 3 via the switches 4to transfer information, like Embodiments 1 and 2. In Embodiment 3, thefixed potential Vp is applied to the gate of the transistor 16, so thatthe transistor 16 is at all times on and is operating in the trioderegion, and the transistor 16 serves as a resistance element. In otherwords, the transistor 16 is equivalent to a resistor between the node 14and the power supply circuit 5. Accordingly, the operation identical tothat of Embodiment 2 can be realized.

By adjusting the potential Vp supplied to the gate of the transistor 16,the level of the node 14 can be controlled, so that the equalizingoperation can be optimized.

Embodiment 4

FIG. 5 is a circuit diagram of a precharge and equalization circuit of afourth embodiment (Embodiment 4). The precharge and equalization circuitof Embodiment 4 comprises a plurality equalizing circuits, all denotedby 10. The equalizing circuits 10 are provided between respective pairsof data lines, all denoted by 1 and 2.

Each of the equalizing circuits 10 is disposed between the correspondingpair of data lines 1 and 2, which are connected to an amplifier, such asa sense amplifier, not shown via switches, in the same way as in FIG. 1,3 or 4. The equalizing circuit 10 comprises first and second switchingelements, in the form of N-channel MOS transistors 11 and 12 havingtheir drains connected to the data lines 1 and 2, respectively, theirsources connected together at the specific potential node 14, and theirgates connected to a common control line 6. The precharge andequalization circuit further comprises third and fourth switchingelements 17 and 18 connected to the respective equalization circuits,and are disposed between the corresponding pair of data lines 1 and 2.First terminals of the switching elements 17 and 18 are connected to thenode 14. A second terminal of the switching element 17 is connected tothe power supply circuit 5 supplying the equalizing potential HVcc(Vcc/2). A second terminal of the switching element 18 is connected to asecond, or precharge potential power supply circuit 8 supplying aprecharge potential VPL. The potential VPL is set be lower than HVcc andis higher than ground potential (GND).

The power supply circuits 5 and 8 are provided in common for a pluralityof equalizing circuits, and connected to the plurality of the third andfourth switches 17 and 18 for the respective equalizing circuits 10.

The switching elements 17 and 18 may be formed of transistors, such asN-channel MOS transistors. In such a case, the second control signalsare applied to the gates of the transistors; to control their conductionand non-conduction.

The operation of this embodiment will next be described with referenceto FIG. 6. First, the pair of data lines 1 and 2 are driven by anamplifier, such as a sense amplifier, not shown, for the purpose ofinformation transfer, and respectively set at the Vcc level and the GNDlevel. The control line 6 is at the Low (GND) level. Accordingly, thetransistors 11 and 12 are off. The switching element 18 is on, and theswitching element 17 is off. The potential of the node 14 is at VPL.

When information transfer is completed, the amplifier, such as a senseamplifier, not shown, is isolated from the pair of data lines, and thepotential level of the control line 6 is raised to the High level, tocommence the equalizing operation in preparation for the next cycle ofdata transfer operation. That is, when the control line 6 exceeds thethreshold potential Vth of the transistor 12, the transistor 12 isturned on, to raise the potential level of the data line 6. At the sametime, the node 14 is at the precharge potential VPL, lower than theequalizing potential HVcc, so that when the potential level of thecontrol line 6 exceeds VPL +Vth, (Vth being the threshold of thetransistor 11,) the transistor 11 is turned on and the level of the dataline 1 is lowered. After that, at a predetermined timing, the switchingelement 18 is turned off, and the switching element 17 is turned on, toequalize the pair of data lines to the potential HVcc.

In this embodiment, before the commencement of the equalizing operation,the node 14 is set at a potential VPL lower than the equalizingpotential, and the on-resistances of the transistors 11 and 12 at thetime of commencement of the equalization are made equal to each other.Accordingly, the operation is quicker than in the case of Embodiment 1to Embodiment 3 in which the MOS transistor connected to the data linehaving the GND potential is turned on, to lower the node 14.

Moreover, it is desirable that the second power supply circuit 8 has alarger driving capability than the first potential power supply circuit5 to quickly precharge the node 14, and thereby expedite the conductionof the switching elements 11 and 12.

In addition, the power consumption can be reduced. Furthermore, sincethe equalizing circuit is formed of an N-channel transistors, the areaoccupied by the device as a whole can be reduced.

The precharge potential power supply circuit 8 may be formed as shown inFIG. 7. The illustrated power supply circuit 8 provides a potential VPLlower than the equalizing potential HVcc and higher than the groundpotential (GND). This power supply circuit 8 comprises two comparators32 and 33, and resistance elements 33 and 34. The positive terminal ofthe comparator 32 is connected to a signal line 31 for supplying thepotential Vcc, and the negative terminal of the comparator 32 isconnected to one end of the resistance element 33, and the output of thecomparator 32. The other end of the resistance element 33 is connectedto one end of the resistance element 34 and the positive terminal of thecomparator 36, and the other end of the resistance element 34 isconnected to the ground. The negative terminal of the comparator 36 isconnected to the output signal line 37 of the comparator 36. The outputof the comparator 36, at its output signal line 37 provides thepotential VPL.

Embodiment 5

FIG. 8 shows another embodiment (Embodiment 5). This embodiment issimilar to Embodiment 4, but the switching elements 17 and 18 are norprovided for the respective equalizing circuits 10, but are provided incommon for a plurality of equalizing circuits 10, and away from the datalines 1 and 2 and the equalizing circuits 10. Specifically, firstterminals of the switching elements 17 and 18 are connected to the nodes14 of a plurality of equalizing circuits 10. A second terminal of theswitching element 17 is connected to the power supply circuit 5, and asecond terminal of the switching element 18 is connected to the powersupply circuit 8. Thus, the switching element 17 connects, whenconductive, the power supply circuit 5 with the nodes 14 of a pluralityof equalizing circuits 10. The switching element 18 connects, whenconductive, the power supply circuit 8 with thee nodes 14 of a pluralityof equalizing circuits 10.

The switching elements 17 and 18 are controlled, in the same way as theswitching elements 17 and 18 in Embodiment 4. The operation of thecircuit of Embodiment 5 is therefore similar to the operation of thecircuit of Embodiment 4.

An additional advantage of this embodiment is that the number of theswitching elements and the number of the wiring conductors of theequalizing circuits can be reduced, and the area occupied by the deviceas a whole can be reduced.

Embodiment 6

FIG. 9 shows another embodiment (Embodiment 6). FIG. 10 is a waveformdiagram showing the operation of the equalizing circuit of FIG. 9. Thisembodiment is similar to Embodiment 6, but the switching elementsforming each equalizing circuit 10 comprise P-channel MOS transistors 21and 22. The gates of the P-channel MOS transistors 21 and 22 areconnected to a common control line 6, the potential on which is loweredto the ground when the transistors 21 and 22 are to be made conductive.

In place of the power supply circuit 8 of Embodiment 4, a power supplycircuit 9 is provided. The power supply circuit 9 provides a potentialVPH which is higher than HVcc and lower than Vcc.

The operation will next be described with reference to FIG. 10. First,for the purpose reading operation, the pair of data lines 1 and 2 aredriven by an amplifier, such as a sense amplifier, not shown, for thepurpose of information transfer, and respectively set at the Vcc leveland the GND level. The control line 6 is at the High (Vcc) level.Accordingly, the transistors 21 and 22 are off. The switching element 18is on, and the switching element 17 is off. The potential of the node 14is therefore at VPH. When information transfer is completed, theamplifier, such as a sense amplifier, not shown, and is isolated fromthe pair of data lines, and the control line 6 is lowered to the Lowlevel, to commence the equalizing operation, in preparation for the nextcycle of data transfer operation. That is, when the control line 6 fallsbelow Vcc-Vtp (Vtp being the threshold of the transistor 21), thetransistor 21 is turned on, to lower the potential level of the dataline 1. At the same time, the node 14 is at the precharge potential VPH,higher than the equalizing potential HVcc, so that when the control line6 falls below VPH-Vtp, (Vtp being the threshold of the transistor 22)the transistor 22) is turned on and the level of the data line 2 israised. After that, at a predetermined timing, the switching element 18is turned off, and the switching element 17 is turned on, to equalizethe pair of data lines 1 and 2 to the potential HVcc.

This configuration replaces the MOS transistors contained in eachequalizing circuit of FIG. 5 with P-channel MOS transistors, and yetrealizes similar operations. In this embodiment, like FIG. 5, (althoughthe equalizing circuit of FIG. 5 uses a low VPL), before thecommencement of the equalizing operation, the circuit is in a stand-bystate, in which the node 14 is set at a potential VPH higher than theequalizing potential, and high-speed equalization is achieved, by havingthe on-resistances of the transistors 21 and 22 at the time ofcommencement equal to each other. Moreover, since the equalizingcircuits are formed of P-channel MOS transistors, if the equalizingpotential is set near Vcc to eliminate the effects of noises of the GNDlevel, equalization of an even higher speed can be achieved.

Embodiment 7

FIG. 11 shows another embodiment (Embodiment 7). This embodiment issimilar to Embodiment 6, but the switching elements 17 and 18 areprovided in common for a plurality of equalizing circuits 10, and awayfrom the data lines 1 and 2, and the equalizing circuits 10.Specifically, first terminals of the switching elements 17 and 18 areconnected to the nodes 14 of a plurality of equalizing circuits 10. Asecond terminal of the switching element 17 is connected to the powersupply circuit 5, and a second terminal of the switching element 18 isconnected to the power supply circuit 9. Thus, the switching element 17connects, when conductive, the power supply circuit 5 with the nodes 14of a plurality of equalizing circuits 10. The switching element 18connects, when conductive, the power supply circuit 8 with the nodes 14of a plurality of equalizing circuits 10.

The switching elements 17 and 18 are controlled, in the same way as theswitching elements 17 and 18 in Embodiment 6. The operation of thecircuit of Embodiment 7 is therefore similar to the operation of thecircuit of Embodiment 6.

An additional advantage of this embodiment is that the number of theswitching elements and the number of the wiring conductors of theequalizing circuits can be reduced, and the area occupied by the deviceas a whole can be reduced.

Modifications

The invention is not limited to the embodiments described above. Theswitching elements may be all formed of transistors. If the transistorsare all of the same channel type, fabrication of the device is simpler.

The inventive concept described in connection with Embodiments 1 to 3can also be applied to a situation where the switching elements of theequalizing circuit are formed of P-channel MOS transistors. In such acase, the control signal is at a high level when it is in an activestate, and is at a low level when it is in an inactive state. As thepotential of the control signal line is lowered (below a threshold ofthe MOS transistor) one of the MOS transistors (first MOS transistor)connected to one of the data lines which has transferred the signal of ahigher potential level is made conductive, so that the potential of thespecific potential supplying node is raised. Because of the potentialincrease in the specific potential supplying node, the MOS transistor(second MOS transistor) connected to the data line having a lowerpotential is made conductive when the potential of the control signalbecomes sufficiently low. The potential sufficiently low to turn on thesecond MOS transistor is the sum of the threshold of the transistor andthe potential of the specific potential supplying node, which is higherthan if the specific potential supplying node is fixed at the equalizingpotential. Accordingly, the MOS transistors are made conductive in ashorter time, than if the specific potential supplying node iS notisolated from the equalizing power supply circuit.

What is claimed is:
 1. A semiconductor memory device comprising:a pairof data lines for transferring complementary signals; an equalizingcircuit having a first switching element connected between one of saidpair of data lines and a node, and a second switching element connectedbetween the other of said pair of data lines and the node, said firstand second switching elements being made conductive in accordance with afirst control signal to electrically connect said pair of data lineswith each other: a power transmitting circuit connecting said node witha supply circuit of an equalizing potential; and a sense amplifierselectively connected to said pair of data lines.
 2. The semiconductormemory device as set forth in claim 1 wherein said sense amplifierconnects to said pair of data lines when said first and second switchingelements are made nonconductive.
 3. The semiconductor memory device asset forth in claim 1 wherein said power transmitting circuit connectssaid node with said supply circuit after said first and second switchingelements are made conductive.
 4. The semiconductive memory device as setforth in claim 1, whereinsaid first control signal is in an active stateto make the first and second Switching elements conductive, and in aninactive state to make the first and second switching elementsnonconductive; said power transmitting circuit comprises a MOStransistor having a first electrode connected to said node, a secondelectrode connected to said supply circuit, and a gate electrode towhich a second control signal is applied; and said second control signalmakes said MOS transistor nonconductive while said first control signalchanges from the inactive state to the active state, and makes said MOStransistor conductive after said first and second switching elements aremade conductive.
 5. The semiconductor memory device as set forth inclaim 1 wherein said power transmitting circuit comprises a resistanceelement having a first end connected to said node, and a second endconnected to said supply circuit.
 6. The semiconductor memory device asset forth in claim 1 wherein said resistance element comprises a MOStransistor having a first electrode connected to said node, a secondelectrode connected to said power supply circuit, and a gate electrodeconnected to such a fixed potential that it operates in the trioderegion.
 7. The semiconductor memory device as set forth in claim 1wherein said first and second switching elements of said equalizingcircuit comprises MOS transistors having their gate electrodes connectedto receive said first control signal.
 8. The semiconductor memory deviceas set forth in claim 1, wherein said equalizing potential is half theVcc level.